VLSI Design

Course Syllabus

MODULE1 - DIGITAL DESIGN

  • Introduction to Digital logic
  • Number Systems
  • Boolean algebra
  • Boolean minimization
  • Combinational circuit design
  • Sequential circuit design
  • Finite state machines
  • Designing complex digital circuits
  • Logic families
  • Miscellaneous concepts

MODULE2- ADVANCED VERILOG

  • Language Introduction
  • Levels of abstraction
  • Module, Ports types and declarations
  • Registers and nets, Arrays
  • Identifiers, Parameters
  • Relational, Arithmetic, Logical, Bit-wise shift Digital system design
  • Simulation & Synthesis issues
  • Unwanted Latches
  • Clock-gating
  • Clock-domain crossing issues
  • Low power techniques
  • RTL Design strategies
  • Operators
  • Writing expressions
  • Behavioral Modeling
  • Structural Coding
  • Continuous Assignments
  • Procedural Statements
  • Always, Initial Blocks, begin ebd, fork join
  • Blocking and Non-blocking statements
  • Operation Control Statements
  • If, case
  • Loops: while, for-loop, for-each, repeat
  • Combination and sequential circuit designs
  • Memory modeling , state machines
  • CMOS gate modeling
  • Writing Tasks
  • Writing Functions
  • Compiler directives
  • Conditional Compilation
  • System Tasks
  • Gate level primitives
  • User defined primitives
  • Delays, Specify block
  • Testbenchs, modeling, timing checks
  • Code for synthesis
  • Advanced topics

MODULE 3- VHDL

  • VHDL Overview and Concepts
  • Levels of Abstraction
  • Entity, Architecture
  • Data Types and declaration
  • Enumerated Data Types
  • Relational, Logical, Arithmetic Operators
  • Signal and Variables, Constants
  • Process Statement
  • Concurrent Statements
  • When-else, With-select
  • Sequential Statement
  • If-then-else, Case
  • Slicing and Concatenation
  • Loop Statements
  • Delta Delay Concept
  • Arrays, Memory Modeling, FSM
  • Writing Procedures
  • Writing Functions
  • Behavioral / RTL Coding
  • Operator Overloading
  • Structural Coding
  • Component declarations and installations
  • Generate Statement
  • Configuration Block
  • Libraries, Standard packages
  • Local and Global Declarations
  • Package, Package body
  • Writing Test Benches
  • Assertion based verification
  • Files read and write operations
  • Advanced topics

MODULE 4 - OVERVIEW OF ASIC EDA FLOW

  • Logic Synthesis Concepts
  • Basic Timing Concepts
  • Fixing Setup, Holdtime violations
  • Formal Verification
  • Design-For-Testability
  • BIST
  • Placement
  • Routing
  • Floorplanning
  • Parasitic Extraction
  • Back-Annotation
  • GDS-II

MODULE5 - ADVANCED FPGA IMPLEMENTATION

  • Logic Synthesis Concepts
  • Basic Timing Concepts
  • Fixing Setup, Holdtime violations
  • Formal Verification
  • Design-For-Testability
  • BIST
  • Placement
  • Routing
  • Floorplanning
  • Parasitic Extraction
  • Back-Annotation
  • GDS-II
  • Evolution of Programmable logic
  • FPGAs Vs ASICs
  • Xilinx FPGA Architecture
  • Essential Building blocks
  • LUT
  • Slices
  • CLBs
  • Block Memories
  • Multipliers
  • Clock Management components
  • Processor
  • IO Pins
  • FPGA Design flow & Implementation
  • Reading reports
  • Pin Assignments
  • Timing & Area Constraints
  • DCMs
  • Power estimation
  • Floorplanning the design
  • Back-annotation simulations
  • FPGA Board Overview
  • Code for complex FPGA and ASICs
  • Generics and Generic maps
  • On-board stimulus generation

MODULE 6- CMOS

  • MOS Fundamentals and Characterization
  • NMOS/PMOS/CMOS Technologies
  • Fabrication Principles
  • Different Styles of Fabrication for NMOS/PMOS/CMOS
  • Design with CMOS Gates
  • Characterization of CMOS Circuits
  • Scaling Effects
  • Sub-Micron Designs
  • Parasitic Extraction and Calculations
  • Subsystem Design
  • Layout Representation for CMOS Circuits
  • Design Exercise using CMOS
  • Introduction of IC Design
  • Different Methodologies for IC Design
  • Fabrication Flows and Fundamentals

State-of-art VLSI CAD tools

  • FPGA tool suites – Xilinx
  • Modelsim-Mentorgraphics Tool

Hardware tools

  • Xilinx Spartan3E FPGA Board

List of Experiments using Verilog

  • 01 Half adder, Full adder, Subtractor
  • 02 4bit comparator & Parity generator
  • 03 8:1 multiplexer
  • 04 Decoder and encoder
  • 05 Flip Flops, 8 bit shift register
  • 06 Bit up/down counter with load able count
  • 07 Test bench for a full adder
  • 08 Barrel shifter

List of Experiments using VHDL

  • 01 Half adder, Full adder, Subtractor
  • 02 4 bit comparator, Parity generator
  • 03 8:1 multiplexer
  • 04 Decoder and encoder
  • 05 Flip Flops, 8 bit shift register
  • 06 Bit up/down counter with load able count
  • 07 Test bench for a full adder
  • 08 Barrel shifter