VLSI Projects

S.No
Titles

PTVL001

A 3.9 ps Time-interval RMS Precision Time-to-Digital Converter using a Dual-sampling Method in an UltraScale FPGA

PTVL002

On the Implementation of Time-Multiplexed Frequency-Response Masking Filters

PTVL003

An Improved DCM-based Tunable True Random Number Generator for Xilinx FPGA

PTVL004

Area-Delay Efficient Digit-Serial Multiplier Based on k-Partitioning Scheme Combined With TMVP Block Recombination Approach

PTVL005

A FPGA-based Unscented Kalman Filter for System-On-Chip Applications

PTVL006

Low-Power/Cost RNS Comparison via Partitioning the Dynamic Range

PTVL007

Elliptic Curve Cryptography with Efficiently Computable Endomorphisms and Its Hardware Implementations for the Internet of Things

PTVL008

SPACE: Semi-Partitioned CachE for Energy Efficient, Hard Real-Time Systems

PTVL009

Fast Predictive Handshaking in Synchronous FPGAs for Fully Asynchronous Multi-Symbol Chip Links. Application to SpiNNaker 2-of-7 Links

PTVL010

A High Throughput List Decoder Architecture for Polar Codes

PTVL011

A High-Throughput Energy-Efficient Implementation of Successive Cancellation Decoder for Polar Codes Using Combinational Logic

PTVL012

A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding

PTVL013

Demonstrating HW-SW Transient Error Mitigation on the single-chip cloud computer data plane

PTVL014

Enhanced Memory reliability against multiple cell upsets using Decimal Matrix code

PTVL015

Wear out Resilience in NOCs through an Aging Aware Adaptive Routing Algorithm

PTVL016

High-Performance H.264/AVC Intra-Prediction Architecture for Ultra

High Definition Video Applications

PTVL017

On-Chip Memory Hierarchy in one Coarse-Grained Reconfigurable Architecture to compress memory space and to reduce time

PTVL018

A Voltage based Leakage current calculation scheme and its application to Nanoscale and FinFET Standard cell designs

PTVL019

High Throughput and Low complexity BCH decoding Architecture for Solid-State Drives

PTVL020

Nonbinary LDPC Decoder based on Simplified Enhanced Generalized Bit-Flipping Algorithm

PTVL021

A 2-D Interpolation based ORD Processor with Partial Layer Mapping for MIMO-OFDM Systems

PTVL022

Digitally controlled Pulse Width Modulator for On-Chip Power Management

PTVL023

UNION: A Unified Inter/Intrachip Optical Network for Chip Multiprocessors

PTME024

Fabrication of Peltier air cooler cum heater

PTVL024

High-Throughput Multistandard Transform Core supporting MPEG/H.264/VC-1 using Common Shared Distributed Arithmetic

PTVL025

Alogirthm and Architecture for a Low-Power Content Addressable Memory based on Sparse Clustered Networks

PTVL026

A Variation-Aware Preferential Design approach for Memory- Based Reconfigurable Computing

PTVL027

Asynchronous Domino Logic Pipeline Design Based on Constructed Critical data path

PTVL028

Low-Power Digital Signal Processor Architecture for Wireless Sensor Nodes

PTVL029

Application Mapping Onto Mesh-Based Network-On-Chip using Discrete Particle Swarm Optimization

PTVL030

Novel Reconfigurable Hardware Architecture for Polynomial Matrix Multiplications

PTVL031

Single-Bit Pseudo Parallel Processing Low-oversampling Delta-Sigma Modulator suitable for SDR Wireless Transmitters


2013 IEEE TITLES

S.No
Titles

PHVL001

A Low-Complexity Turbo Decoder Architecture for Energy-Efficient Wireless Sensor Networks

PHVL002

Pipelined Radix- Feedforward FFT Architectures

PHVL003

Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip

PHVL004

STBC-OFDM Downlink Baseband Receiver for Mobile WMAN

PHVL005

Low Latency Systolic Montgomery Multiplier for Finite Field GF(2^m) Based on Pentanomials

PHVL006

Architecturally Homogeneous Power-Performance Heterogeneous Multicore Systems

PHVL007

Reconfigurable Accelerator for the Word-Matching Stage of BLASTN

PHVL008

Reconfigurable Adaptive Singular Value Decomposition Engine Design for High-Throughput MIMO-OFDM Systems

PHVL09

MDC FFT/IFFT Processor With Variable Length for MIMO-OFDM Systems

PHVL010

Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops

PHVL011

135-MHz 258-K Gates VLSI Design for All-Intra H.264/AVC Scalable Video Encoder

PHVL012

Fpga Design of Digit-Serial FIR Filters: Algorithms,Architectures, and a CAD Tool

PHVL013

A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS Technology

PHVL014

CORDIC Designs for Fixed Angle of Rotation

PHVL015

A Unified Graphics and Vision Processor With a 0.89 W/fps Pose Estimation Engine for Augmented Reality

PHVL016

A Low-Cost, Systematic Methodology for Soft Error Robustness of Logic Circuits

PHVL017

Performance Analysis of μ-law Companding & SQRT Techniques for M-QAM OFDM Systems

PHVL018

Low Power and Memory Efficient FFT Architecture Using Modified CORDIC Algorithm


2012 IEEE TITLES

S.No
Titles

PHVL001

BPSK system on Spartan 3E FPGA

PHVL002

Implementation of PSK and QAM demodulators on FPGA

PHVL003

Design and simulation of 32-point FFt using Radix-2 algorithm for FPGA implementation

PHVL004

Platform independent customizable UART soft-core

PHVL005

VLSI architecture of arithmetic coder used in SPIHT

PHVL006

Ultralow-voltage process variation Tolerant Schmitt-Trigger based SRAM design

PHVL007

Single Phase clocked Quasi Static Adiabatic Tree adder

PHVL008

Enhanced power gating schemes for low leakage low ground bounce noise in Deep submicron circuits.

PHVL09

Low-power pulse-triggered flip-flop design with conditional pulse-enhancement scheme

PHVL010

Design of Low voltage low power operational amplifier

PHVL011

A novel architecture for vlsi implementation of RSA cryptosystem

PHVL012

FPGA hardware of the LSB steganography method

PHVL013

A Fast cryptography pipelined hardware developed in FPGA with VHDL

PHVL014

An efficient FPGA implementation of the advanced Encryption standard algorithm

PHVL015

A novel data embedding method using adaptive pixel pair matching

PHVL016

VHDL implementation of a flexible and synthesizable FFT Processor

PHVL017

Design of Modified Low power booth multiplier

PHVL018

An Efficient VLSI architecture for Lifting based Discrete Wavelet Transform

PHVL019

A novel architecture for an efficient implementation of image compression using 2D-DWT

PHVL020

QPSK modulator on FPGA

PHVL021

Implementation of a QPSK system on FPGA

PHVL022

Simulation and Implementation of a BPSK modulator on FPGA

PHVL023

Hardware efficiency comparison of AES implementations

PHVL024

Efficient design and implementation of FFT

PHVL025

Low-power and area-efficient carry select adder

PHVL026

A pipeline architecture for fast computation of the 2-D Discrete wavelet transform

PHVL027

FPGA implementation of AES algorithm

PHVL028

A Pipleline VLSI Architecture for high-speed computation of the 1-D Discrete Wavelet Transform

PHVL029

Design of pipelined FFT processor based on FPGA

PHVL030

An FPGA-based architecture for linear and morphological image filtering

PHVL031

Performance Evaluation of DES and Blowfish Algorithms

PHVL032

Unified Current-Source Control for Low-Power Current-Mode-Logic Bit-Serial Circuits

PHVL033

Fast Linear Model Predictive Control Via Custom Integrated Circuit Architecture

PHVL034

Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-Recovery Logic

PHVL035

High-Throughput Efficient Non-Binary LDPC Decoder Based on the Simplified Min-Sum Algorithm

PHVL036

Pipelined Parallel FFT Architectures viaFolding Transformation

PHVL037

Resource Efficient Implementation of Low Power MB-OFDM PHY Baseband Modem With Highly Parallel Architecture

PHVL038

The LUT-SR Family of Uniform Random Number Generators for FPGA Architectures

PHVL039

On Practical Implementation and Generalizations of Max Operator for Turbo and LDPC Decoders

PHVL040

A Highly Efficient VLSI Architecture for H.264/AVC Level 5.1 CABAC Decoder

PHVL041

Throughput/Resource-Efficient Reconfigurable Processor for Multimedia Applications

PHVL042

A fault tolerant parallel-prefix adder for VLSI and FPGA design

PHVL043

A high throughput sort free VLSI architecture for wireless applications

PHVL044

A novel architecture for VLSI implementation of RSA cryptosystem

PHVL045

A novel VLSI architecture for generation of Six Phase pulse compression sequences

PHVL046

A Pipeline VLSI Architecture for Fast Computation of the 2-D Discrete Wavelet Transform

PHVL047

An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform

PHVL048

Area and power efficient VLSI architecture for DCT

PHVL049

Area-Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of Odd Length Based on Fast FIR Algorithm

PHVL050

Design of low power high speed VLSI adder subsystem

PHVL051

Efficient VLSI implementation of soft-input soft-output fixed-complexity sphere decoder

PHVL052

Highly secured high throughput VLSI architecture for AES algorithm

PHVL053

Implementation of VLSI-oriented FELICS algorithm using Pseudo Dual-Port RAM

PHVL054

Novel VLSI architecture for two-dimensional radon transform computations

PHVL055

VLSI Architecture for a Reconfigurable Spectrally Efficient FDM Baseband Transmitter

PHVL056

VLSI Based Robust Router Architecture

PHVL057

VLSI design of power efficient Carry Skip Adder using TSG & Fredkin reversible gate

PHVL058

VLSI Implementation of Advanced Encryption Standard

PHVL059

VLSI signal processing oriented segmentation based serial parallel multiplier

PHVL060

A Hippocampal Cognitive Prosthesis:Multi-Input, Multi-Output Nonlinear Modeling and VLSI Implementation

PHVL061

VLSI Architecture for a Reconfigurable Spectrally Efficient FDM Baseband Transmitter

PHVL062

VLSI Implementation of a Bio-Inspired Olfactory Spiking Neural Network

PHVL063

A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores