c Photon Technologies - Verilog projects in Chennai

Verilog projects in chennai

S.No
Titles

PHVL001

BPSK system on Spartan 3E FPGA

PHVL002

Implementation of PSK and QAM demodulators on FPGA

PHVL003

Design and simulation of 32-point FFt using Radix-2 algorithm for FPGA implementation

PHVL004

Platform independent customizable UART soft-corePlatform independent customizable UART soft-core

PHVL005

VLSI architecture of arithmetic coder used in SPIHT

PHVL006

Ultralow-voltage process variation Tolerant Schmitt-Trigger based SRAM design

PHVL007

Single Phase clocked Quasi Static Adiabatic Tree adder

PHVL008

Enhanced power gating schemes for low leakage low ground bounce noise in Deep submicron circuits.

PHVL09

Low-power pulse-triggered flip-flop design with conditional pulse-enhancement scheme

PHVL010

Design of Low voltage low power operational amplifier

PHVL011

A novel architecture for vlsi implementation of RSA cryptosystem

PHVL012

FPGA hardware of the LSB steganography method

PHVL013

A Fast cryptography pipelined hardware developed in FPGA with VHDL

PHVL014

An efficient FPGA implementation of the advanced Encryption standard algorithm

PHVL015

A novel data embedding method using adaptive pixel pair matching

PHVL016

VHDL implementation of a flexible and synthesizable FFT Processor

PHVL017

Design of Modified Low power booth multiplier

PHVL018

An Efficient VLSI architecture for Lifting based Discrete Wavelet Transform

PHVL019

A novel architecture for an efficient implementation of image compression using 2D-DWT

PHVL020

QPSK modulator on FPGA

PHVL021

Implementation of a QPSK system on FPGA

PHVL022

Simulation and Implementation of a BPSK modulator on FPGA

PHVL023

Hardware efficiency comparison of AES implementations

PHVL024

Efficient design and implementation of FFT

PHVL025

Low-power and area-efficient carry select adder

PHVL026

A pipeline architecture for fast computation of the 2-D Discrete wavelet transform

PHVL027

FPGA implementation of AES algorithm

PHVL028

A Pipleline VLSI Architecture for high-speed computation of the 1-D Discrete Wavelet Transform

PHVL029

Design of pipelined FFT processor based on FPGA

PHVL030

An FPGA-based architecture for linear and morphological image filtering

PHVL031

Performance Evaluation of DES and Blowfish Algorithms

PHVL032

Unified Current-Source Control for Low-Power Current-Mode-Logic Bit-Serial Circuits

PHVL033

Fast Linear Model Predictive Control Via Custom Integrated Circuit Architecture

PHVL034

Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-Recovery Logic

PHVL035

High-Throughput Efficient Non-Binary LDPC Decoder Based on the Simplified Min-Sum Algorithm

PHVL036

Pipelined Parallel FFT Architectures viaFolding Transformation

PHVL037

Resource Efficient Implementation of Low Power MB-OFDM PHY Baseband Modem With Highly Parallel Architecture

PHVL038

The LUT-SR Family of Uniform Random Number Generators for FPGA Architectures

PHVL039

On Practical Implementation and Generalizations of Max Operator for Turbo and LDPC Decoders

PHVL040

A Highly Efficient VLSI Architecture for H.264/AVC Level 5.1 CABAC Decoder

PHVL041

Throughput/Resource-Efficient Reconfigurable Processor for Multimedia Applications

PHVL042

A fault tolerant parallel-prefix adder for VLSI and FPGA design

PHVL043

A high throughput sort free VLSI architecture for wireless applications

PHVL044

A novel architecture for VLSI implementation of RSA cryptosystem

PHVL045

A novel VLSI architecture for generation of Six Phase pulse compression sequences

PHVL046

A Pipeline VLSI Architecture for Fast Computation of the 2-D Discrete Wavelet Transform

PHVL047

An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform

PHVL048

Area and power efficient VLSI architecture for DCT

PHVL049

Area-Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of Odd Length Based on Fast FIR Algorithm

PHVL050

Design of low power high speed VLSI adder subsystem

PHVL051

Efficient VLSI implementation of soft-input soft-output fixed-complexity sphere decoder

PHVL052

Highly secured high throughput VLSI architecture for AES algorithm

PHVL053

Implementation of VLSI-oriented FELICS algorithm using Pseudo Dual-Port RAM

PHVL054

Novel VLSI architecture for two-dimensional radon transform computations

PHVL055

VLSI Architecture for a Reconfigurable Spectrally Efficient FDM Baseband Transmitter

PHVL056

VLSI Based Robust Router Architecture

PHVL057

VLSI design of power efficient Carry Skip Adder using TSG & Fredkin reversible gate

PHVL058

VLSI Implementation of Advanced Encryption Standard

PHVL059

VLSI signal processing oriented segmentation based serial parallel multiplier

PHVL060

A Hippocampal Cognitive Prosthesis: Multi-Input, Multi-Output Nonlinear Modeling and VLSI Implementation

PHVL061

VLSI Architecture for a Reconfigurable Spectrally Efficient FDM Baseband Transmitter

PHVL062

VLSI Implementation of a Bio-Inspired Olfactory Spiking Neural Network

PHVL063

A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores